March 21, 2017

Software-Defined Radio

A software-defined radio (SDR) system is a radio communication system which can tune to any frequency band and receive any modulation across a large frequency spectrum by means of a programmable hardware which is controlled by software[i].”

SDR is a powerful solution with application in the following scenarios[ii]:

  • when communication standards are quickly changing or they are uncertain
  • where a software (SW) module (IP core) can run on multiple hardware (HW) platforms
  • when SW modules need to be changed or updated over-the-air
  • when a single HW platform can run multiple SW modules
  • where device cost and HW complexity must be reduced

In an SDR architecture, the baseband processing, waveform generation, and signal processing may be controlled and defined by software, in real-time. SDR systems can be deployed in customized platforms using Commercial-Off-The Shelf (COTS) HW, which reduces the time to integrate and deploy new radio solutions[iii],[iv].

TWEVO’s Architecture

TWEVO has developed a modular architecture, fully pipelined, with distributed control and parallel processing. The distributed control model relaxes the synchronization requirements by restricting the timing constraints to small synchronous islands. This simplifies the simultaneous processing of multiple blocks, exploiting the parallelism of the architecture and enabling implementation of asynchronous computational demanding processes.

Baseband processing refers to the operations used to generate, codify, and protect data symbols (bit streams), which are conveyed and retrieved through analogue signals. TWEVO’s architecture comprises the following software-based baseband processing blocks:

  • A configurable modulator/demodulator implementing QPSK, 16QAM, 64QAM and 256QAM.
  • A frequency domain (FD) framing/de-framing to shape the transmitted signal spectrum.
  • IFFT/FFT processing blocks to render the frame into the time/frequency domain.
  • A Carrier Frequency Offset (CFO) estimation block that provides timing synchronization.
  • A CFO compensation module that removes the estimated frequency offset.
  • A Channel estimator block to acquire channel state information.
  • Filters and equalizers to compensate the channel distortion.

At the lowest architecture level, the architecture adopts interconnecting FIFOs[v] between each processing block, reducing the signalling and control paths. This also allows the implementation of complex designs operating at higher clock rates. The figure below illustrates how each processing block has an associated FIFO which receives and delivers the data flow to the neighbour processing blocks. The adoption of such architecture allows the agile design, development and standalone testing of new processing blocks in the SDR baseband processing chain.

The building block in TWEVOS’s asynchronous architecture is comprised by a processing block and its associated FIFO.

At the radio level, the strict synchronicity of the OFDM transmitter and receiver can be limited to the ADC and DAC, which significantly relaxes the architecture timing constraints. The transceivers’ synchronicity is achieved when the following conditions are meet: first, the baseband transmitter must ensure that the DAC interfacing FIFO does not get empty; second, the ADC of the baseband receiver which is interfaced with a FIFO does not get full. Following this approach the whole transceiver design has been built as a set of interconnected modules (one processing block and its FIFO) with similar interfaces, i.e., a SDR assembled in a “drag-and-dropped” fashion.

The general REVOsdr’s architecture has several independent clock domains, as shown in the following figure: transmitter, receiver and RF board interface. Such a domain splitting enables the control of the clock trees and limits the RF clock domain strictly to the area within the FPGA that holds the RF board interface block. The transmitter and receiver are self-contained and their performance is mainly independent of the adopted RF board and its clocking structure.

Clock domains across baseband functions and support hardware boards

REVOsdr’s architecture has a minimum dependency on the circuit’s extension due to the decentralized control and parallel processing. The overall throughput is limited by the block with the lowest throughput in the transceiver chain and the remaining processing blocks have limited impact in the overall performance.

[i] SDR Forum, “SDR Market Study: The Cognitive Radio Market,” TX, USA, 2007.

[ii] Gartner Research, “Hype Cycle for Embedded Software and Systems,” 2015

[iii] Wireless Innovation Forum, “Business Models for New Entrants in the SDR Tactical Radio Market (WINNF-13-P-0001-V1.0.0),” 2013.

[iv] Frost & Sullivan, “Software Defined Radio: Technology Penetration and Roadmapping,” 2012.

[v] A FIFO (First-in-first-out) is a method to organize and manipulate data buffers, see Grayver, Implementing Software Defined Radio. Springer, 2013.